Bus communication protocols generally divide bus signals into three groups—address bus signals, control bus signals, and data bus signals.
FIG. 1 a diagram illustrating an exemplary configuration and an exemplary data transmission process of related-art bus signals that are classified into the three groups.
Referring to FIG. 1, when transmitting data, an address signal ADDR representing a destination of data, and a control signal CTRL are transmitted in the first bus cycle. The data signal DAT is transmitted from a next bus cycle.
According to circumstance, there is a bus communication protocol that divides the first bus cycle into two different cycles—an address cycle and a control cycle.
According to another communication protocol, an address signal and a data signal may share one physical bus when the number of signal lines is limited. In this case, one physical bus serves as an address bus in an address cycle, and serves as a data bus in a data transmission cycle.
Thus, in order to transmit information such as an address signal, a control signal, and a data signal, related-art bus communication protocols transmit a data signal in a simple and standardized bus cycle order. However, these related-art bus communication protocols are inefficient because all overlapping data are transmitted in a data transmission process even when adjacent data overlap each other. For example, when a large amount of multimedia data are continuously transmitted, adjacent data carrying partially overlapping contents are frequently transmitted. In this case, the adjacent data having partially overlapping contents are inevitably transmitted as is. This may result in not only a waste of bus bandwidth, but also an increase of bus power consumption.
When various related-art data compression algorithms (for example, entropy coding, variable length coding, code-book coding, arithmetic coding, and the like) are used, wasted bus bandwidth and bus electric power according to the overlapping data transmission are reduced.
However, in order to implement the above data compression algorithms, look-up tables, large-sized buffers, and algorithm processing logics are required. This may lead to costly hardware design and transmission delay due to complex algorithm operation. Moreover, it is inappropriate in terms of cost to apply expensive hardware to a simple bus system to implement the data compression algorithms.
Studies on the bus encoding schemes (for example, differential coding, gray coding, bus invert coding and the like) have been carried out to reduce bus power consumption. The bus encoding schemes encode data values in every bus cycle to reduce the toggling frequency of a signal.
However, because the above encoding schemes are focused only on reducing power consumption, the bus bandwidth is still wasted due to transmission of overlapping data. Also, designs for separate hardware such as additional control signal lines, look-up tables for coding, and temporary buffers inevitably accompany the bus encoding schemes as well as related-art data compression algorithms. Consequently, these bus encoding schemes are not cost-effective.
Accordingly, a method of achieving bus data compression transmission at a minimum cost is required.